November 28, 2023


Step Into The Technology

AMD’s Flagship RDNA3 GPU Rumored to Feature 384-bit Memory Bus

4 min read


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As we head into summer season, a lot more details about AMD’s impending GPU architecture is last but not least coming to light. So far there hasn’t been a good deal of details to peruse, despite there being a deluge of leaks about Nvidia’s programs. To rectify this imbalance, internet sleuths have been poring about the company’s drivers seeking for any morsel of facts they can obtain. They just lately strike pay out dust care of AMD’s linux motorists for GPUs. AMD has because patched the data out of the driver, although seemingly verifying it by performing so.

A Twitter person named Kepler (ironically) was initially to place the element. The driver had a line that was labeled MCD_Occasion_NUM with the quantity 6. This looks to verify six memory controllers. If you extrapolate that to just about every one getting 64-little bit, that equals a 384-bit memory controller. This is an update to the 256-bit bus on its flagship RDNA2 GPUs, the RX 6900/6950 XT. What is appealing is AMD put those people GPUs up against Nvidia’s RTX 3090, which has a 384-bit bus. AMD described a broader bus was not essential, as it experienced a trick up its sleeve: Infinity Cache. In general, AMD was correct. It was in a position to go toe-to-toe in rasterization with Nvidia this round. Despite reaching parity with its rival, it appears to be like AMD isn’t using any chances with RDNA3. AMD also replaced this line of code with diverse text a week later on, according to Videocardz. As usually, deleting the offending textual content just heightens the intrigue.

Twitter user AMDGPU’s mockup of the Navi 31 package. (Picture: @AMDGPU_)

This leak appears to validate the former speculation about the style and design of the chip as nicely. As revealed higher than, it’s extended been rumored to be a seven-chiplet GPU. That means a key graphics chiplet and six multi-cache dies, or MCDs. This could suggest it will activity as substantially as 192MB of Infinity Cache assuming 32MB per die. Kepler also predicts AMD could use 3D stacking on its flagship GPU, doubling that amount to 384MB. If so that would mark a radical enhance in the amount of money of Infinity Cache it’s using. The existing RX 6950 XT has just 128MB.

Also, working with the 6950 XT as a benchmark, we can also be expecting memory bandwidth to be almost double for RDNA3. If it uses the same 18Gb/s GDDR6 as the present-day GPU, it would be capable of 864GB/s. That is compared to the 6950’s 576GB/s highest. It also doesn’t get into account the gains of Infinity Cache either. That would very easily allow for an RDNA3 GPU to obtain 1TB/s of memory bandwidth. This would match the memory bandwidth of Nvidia’s RTX 3090 Ti.

Just one opportunity clarification for AMD’s bandwidth raise lies in the general size of the card. Leading-stop RDNA3 cards have been rumored to discipline up to 12,288 cores. The top rated-conclusion Radeon 6950XT fielded 128MB of L3 cache to back up 5,120 GPU cores. If AMD bumps core counts this high, even a 192MB L3 cache may well not be sufficient. A 384MB L3 would basically raise the whole sum of L3 relative to the range of cores, although a 192MB L3 would even now depict a modest decrease.

Checks of AMD’s memory bandwidth have continually demonstrated that Infinity Cache does cut down tension on memory bandwidth, so irrespective of how substantially cache AMD fields, one detail is clear: If these rumors are legitimate, the business resolved it necessary to use equally memory bandwidth and Infinity Cache to capture up with Nvidia’s all round performance instead than substituting one for the other.

For its portion, Nvidia is also rumored to be raising the cache dimensions on its upcoming Ada Lovelace GPUs. Earlier reports indicated Nvidia would be bumping L2 quantities by 16x, at least on some versions. It’s speculated to be incorporating 16MB of L2 per 64-bit memory controller, for a full of 96MB. It at present uses just 512KB of L2 on its GA102 die with 32-little bit memory controllers. This would mark a important boost in L2 quantities, as Nvidia attempts to blunt AMD’s cache offensive.

As constantly, we will have to wait around and see the place the chips fall when these two titanic GPUs go head-to-head later this calendar year. What is in particular fascinating this time all around is both equally businesses are working with the very same TSMC N5 procedure. This will make for an unparalleled fight of MCM compared to monolithic layouts using the exact same fabrication node. A single concern was brought up not long ago even though, which is that TSMC clients have been seeking to decrease their current orders. This has been in reaction to the current GPU dump that’s happened, as nicely as world economic jitters. Nonetheless, that report mentioned AMD was not inquiring to minimize its purchase of 5nm goods, but Nvidia was. This could direct to a hold off for the RTX 40-series launch. TSMC reportedly instructed Nvidia it cannot lower its get, but it can thrust it back again a bit.

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